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[Applications] ZBT SRAM

Description: 用verilog HDL写的操作SRAM的源码-with Verilog HDL write operation SRAM FOSS
Platform: | Size: 6144 | Author: 刘波 | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[VHDL-FPGA-Verilog] ZBT SRAM控制器参考设计vhdl_xilinx

Description: ZBT SRAM控制器参考设计，xilinx提供的VHDL源代码-ZBT SRAM controller reference design for Xilinx VHDL source code
Platform: | Size: 9216 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] hanbaosram

Description: 德国汉堡大学的SRAM测试代码,使用VHDL编写,供大家参考-University of Hamburg, Germany, SRAM test code, the use of VHDL, for your reference
Platform: | Size: 6144 | Author: 汪涌 | Hits:

[SCM] PinYin_InputMethod_C51

Description: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。 原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。 因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-( 编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。 在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。 打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi
Platform: | Size: 14336 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] FPGA_write_sram

Description: FPGA向SRAM中写入数据，VHDL编程-FPGA to the SRAM write data, VHDL programming
Platform: | Size: 262144 | Author: 简 | Hits:

[Software Engineering] SRAM

Description: 是一个基于VHDL的SRAM程序，很有代表意义，下下吧-Is a VHDL of SRAM-based procedures, is very representative of significance, under the under the bar
Platform: | Size: 3072 | Author: 张俊 | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 静态随机存储器(SRAM)设计VHDL代码，已经生成的了-Static random access memory (SRAM) design of VHDL code, has generated a
Platform: | Size: 345088 | Author: 陆见风 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: LCD控制VHDL程序与仿真和LED控制VHDL程序与仿真,都已调试过了-LCD control procedures and simulation of VHDL and VHDL program LED control and simulation, have been debug
Platform: | Size: 162816 | Author: gillyamylee | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: SRAM编译过的源代码 强烈推荐
Platform: | Size: 3072 | Author: JP | Hits:

[VHDL-FPGA-Verilog] sram+lcd

Description: 用vhdl格式写的sram源代码，把扩展名txt改为.v即可-VHDL format used to write the SRAM source code, to be re-txt extension. V can
Platform: | Size: 2048 | Author: 郭艳红 | Hits:

[VHDL-FPGA-Verilog] sram

Description: FPGA向SRAM中写入数据(VHDL编程)，包含通用fifo，sram等-FPGA to the SRAM write data (VHDL programming), contains general fifo, sram, etc.
Platform: | Size: 270336 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] SRAM-PINGPANG

Description: 超声视频图像需要实时地采集并在处理后在显示器上重建，图像存储器就必须不断地写入数据，同时又要不断地从存储器读出数据送往后端处理和显示[11]。为了满足这种要求，可以在采集系统中设置2片容量一样的SRAM，通过乒乓读写机制来管理。任何时刻，只能有1片SRAM处于写状态，同时也只有1片SRAM处于读状态。工作期间，2片SRAM都处于读写状态轮流转换的过程，转换的过程相同，但是状态错开，从而保证数据能连续地写人和读出祯存.-Real-time ultrasound video images need to collect and deal with the reconstruction after the display, image memory must be continually write data, while at the same time continuously sent from the memory读出数据back-end processing and display [11]. To meet this requirement, you can set up collection system capacity of two different SRAM, read and write through the ping-pong mechanisms to manage. At any time, can only have a SRAM in write state, but also the only one at a time the state of SRAM. Work, two SRAM read and write are in the process of converting a state of rotation, the conversion process of the same, but the state staggered to ensure that data can be continuously written and read out Qizhen depositors.
Platform: | Size: 1024 | Author: smj1980 | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 使用方法： SRAM编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: SRAM programming, copied to the hard drive, open the project file with ISE can
Platform: | Size: 10240 | Author: yhz | Hits:

[Other] sram

Description: 对常用的sram完成读写控制，可以根据具体地址增加参数，非常灵活-Commonly used to read and write sram to complete control, can be increased in accordance with the specific parameters of address, a very flexible
Platform: | Size: 144384 | Author: yaodi | Hits:

[Other] sram

Description: to write and read from an sram. its actually a logic cell,when the write enable is high its possible to write data onto a memory location when read enable is high we can read the data in given memory location
Platform: | Size: 37888 | Author: mariamma | Hits:

[VHDL-FPGA-Verilog] sram

Description: 基于FPGA的SRAM控制程序，里面附加了在线逻辑分析功能的程序，调试时相当的方便-SRAM-based FPGA-control program, which added an online feature of the program logic analysis, debugging very convenient when
Platform: | Size: 1752064 | Author: 李成有 | Hits:

[VHDL-FPGA-Verilog] sram

Description: 数据存储和读取电路以一个双端口SRAM为中心，用二进制计数器产生存取地址、以十进制计数器产生欲存储的数据，读出的数据经过LED七段译码，送LED数码管显示-Data storage and reading circuit in a dual-port SRAM as the central access address generated using a binary counter to generate For decimal counter data stored, read out the data through LED seven-segment decoder, sending LED digital display
Platform: | Size: 434176 | Author: william | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it is read and write for IS61LV24516 model, if not required for this type of SRAM timing of the program changes. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 1024 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] sram

Description: 用FPGA 控制sram读写程序的小程序，-fpga control precedure
Platform: | Size: 16384 | Author: lujian | Hits:
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